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NOR Flash Driver
15-3-1 DRIVER ARCHITECTURE
When used with a parallel NOR device, the NOR driver is three layered, as depicted in the
figure below. The generic NOR driver, as always, provides sector abstraction and performs
wear-leveling (to make certain all blocks are used equally). Below this, the physical-layer
driver implements a particular command set to read and program the flash and erase
blocks. Lastly, a BSP implements function to initialize and unitialize the bus interface.
Device commands are executed by direct access to the NOR, at locations appropriately
offset from the configured base address.
NOR Driver
fs_dev_nor.c/h
Provides generic driver interface (e.g.,
init, read, write) and performs wear-
leveling so all blocks are used equally.
Physical-Layer Driver
fs_dev_nor_amd_1x16.*
fs_dev_nor_cfi_intel.*
fs_dev_nor_cfi_sst39.*
Implements particular NOR flash
command set; accesses NOR directly
on bus interface.
Bus interface
BSP
NOR
fs_dev_nor_bsp.c
Initialize/uninitial-
ize bus interface.
Figure 15-2 NOR driver architecture (parallel NOR flash)
15-3-2 HARDWARE
Parallel NOR devices typically connect to a host MCU/MPU via an external bus interface
(EBI), with an 8- or 16-bit data lines and 20 or more address lines (depending on the device
size). Many silicon vendors offer parallel NOR product lines; most devices currently
marketed are conformant to the Common Flash Interface (CFI). A set of query information
allows the μC/FS NOR driver physical-layer drivers to interface with almost any NOR flash
without configuration or modification. The standard query information provides the
following details:
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